In many electronic circuits, charge pump circuits are utilized to generate a positive pumped voltage having an amplitude greater than that of a positive supply voltage, or to generate a negative pumped voltage from the positive supply voltage, as understood by those skilled in the art. For example, in a conventional dynamic random access memory ("DRAM"), a charge pump circuit may be utilized to generate a boosted word line voltage V.sub.CCP having an amplitude greater than the amplitude of a positive supply voltage V.sub.CC, and a negative voltage pump circuit may be utilized to generate a negative substrate or back-bias voltage V.sub.bb that is applied to the bodies of NMOS transistors in the DRAM. Another typical application of a charge pump circuit is the generation of a high voltage utilized to erase data stored in blocks of memory cells or to program data into memory cells in non-volatile electrically block-erasable or "FLASH" memories, as will be understood by those skilled in the art.
FIG. 1 is a schematic of a conventional two-stage charge pump circuit 100 that generates a pumped output voltage V.sub.P having an amplitude greater than the amplitude of a supply voltage source V.sub.CC in response to complementary clock signals CLK and CLK, as will be described in more detail below. The charge pump circuit 100 includes two voltage-boosting stages 102 and 104 connected in series between an input voltage node 106 and an output voltage node 108. The voltage-boosting stage 102 includes a capacitor 110 receiving the clock signal CLK on a first terminal and having a second terminal coupled to the input node 106. A diode-coupled transistor 112 is coupled between the input voltage node 106 and a voltage node 114, and operates as a unidirectional switch to transfer charge stored on the capacitor 110 to a capacitor 116 in the second voltage-boosting stage 104. The capacitor 116 is clocked by the complementary clock signal CLK. A transistor 118 transfers charge stored on the capacitor 116 to a load capacitor C.sub.L when the transistor 118 is activated. A threshold voltage cancellation circuit 122 generates a boosted gate signal V.sub.BG responsive to the CLK and CLK signals, and applies the signal V.sub.BG to control activation of the transistor 118. When the CLK and CLK signals are high and low, respectively, the circuit 122 drives the signal V.sub.BG low to turn OFF the transistor 118, and when the CLK and CLK signals are low and high, respectively, the circuit 122 drives the signal V.sub.BG high to turn ON the transistor 118. The cancellation circuit 122 may be formed from conventional circuitry that is understood by those skilled in the art. The charge pump circuit 100 further includes a diode-coupled transistor 120 coupled between the supply voltage source V.sub.CC and node 106. The diode-coupled transistor 120 operates as a unidirectional switch to transfer charge from the supply voltage source V.sub.CC to the capacitor 110.
A ring oscillator 124 generates an oscillator clock signal OCLK that is applied to a switching circuit 126 coupled between the ring oscillator 124 and a clocking-latching circuit 128. The switching circuit 126 receives a regulation output signal REGOUT from external control circuitry (not shown in FIG. 1), and when the REGOUT signal is inactive low, the switching circuit 126 presents a low impedance and thereby applies the OCLK signal to the clocking-latching circuit 128. When the REGOUT signal is active high, the switching circuit 126 presents a high impedance, which isolates or removes the OCLK signal from the clocking-latching circuit 128. The clocking-latching circuit 128 latches the applied OCLK signal and generates the complementary clock signals CLK and CLK responsive to the latched OCLK signal. The CLK and CLK signals have the same frequency as the OCLK signal, and are complementary signals so there is a phase shift of 180.degree. between these signals.
The operation of the conventional charge pump circuit 100 will now be described in more detail with reference to the timing diagram of FIG. 2, which illustrates the voltages at various points in the charge pump circuit 100 during operation. In operation, the charge pump circuit 100 operates in two modes, a normal mode and a power-savings mode. During both the normal and power-savings modes of operation, the ring oscillator 124 continuously generates the OCLK signal. The charge pump circuit 100 operates in the normal mode when the pumped output voltage V.sub.P is less than a desired pumped output voltage V.sub.PD. When V.sub.P &lt;V.sub.PD, the external control circuitry drives the REGOUT signal inactive low causing the switching circuit 126 to apply the OCLK signal to the clocking-latching circuit 128. In response to the applied OCLK signal, the clocking-latching circuit 128 latches the OCLK and clocks the stages 102 and 104 with the CLK and CLK signals generated in response to the latched OCLK signal.
At just before a time t.sub.0, the CLK signal is low having a voltage of approximately 0 volts and the CLK signal is high having a voltage of approximately the supply voltage V.sub.CC, and each of the voltages on the nodes 106, 114, and 108 and the have assumed values as shown for the sake of example. Also, before the time t.sub.0 the REGOUT signal is inactive low and the circuit 122 drives the boosted gate signal V.sub.BG high responsive to the CLK and CLK signals being low and high, respectively. When the CLK signal is low, the terminal of the capacitor 110 is accordingly at approximately ground and the voltage at the node 106 is sufficiently low to turn ON the diode-coupled transistor 120, transferring charge from the supply voltage source VCC through the transistor 120 to charge the capacitor 110. As shown in FIG. 2, the voltage at the node 106 (i.e., the voltage across the capacitor 110) is increasing just before the time t.sub.0 as the capacitor 110 is being charged. Also just before the time t.sub.0, the voltage at the node 114 equals the high voltage of the CLK signal plus the voltage stored across the capacitor 116 (V.sub.116). This bootstrapped voltage on the node 114 is sufficiently greater than the voltage V.sub.p on the output voltage node 108 to turn ON the transistor 118, transferring charge from the capacitor 116 through the transistor 118 to the load capacitor C.sub.L. As shown, the voltage at node 114 is decreasing and the voltage V.sub.p increasing just before the time to as charge is being transferred through the transistor 118.
At the time t.sub.0, the CLK signal goes high, driving the voltage on the node 106 to the high voltage (V.sub.CC) of the CLK signal plus the voltage stored across the capacitor 110 (V.sub.110). At this point, the voltage on the node 106 is sufficiently high to turn OFF the transistor 120, isolating the node 106 from the supply voltage source V.sub.CC. Also at the time t.sub.0, the CLK signal goes low (to ground), causing the voltage on the node 114 to equal the voltage V.sub.116 stored across the capacitor 116. The voltage on the node 106 is now sufficiently greater than the voltage on the node 114 to turn ON the transistor 112, transferring charge from the capacitor 110 through the transistor 112 to the capacitor 116. As shown in FIG. 2, between the time t.sub.0 and a time t.sub.1, which corresponds to the interval the CLK signal is high and CLK signal is low, the voltage at the node 106 decreases and the voltage at the node 114 increases as charge is pumped or transferred through the transistor 112. It should be noted that during this time, the transistor 118 is turned OFF because the voltage V.sub.p is sufficiently greater than the voltage at the node 114 during normal operation of the charge pump circuit 100.
At the time t.sub.1, the CLK and CLK signals go low and high, respectively, and the charge pump circuit 100 operates in the same manner as previously described for just before the time t.sub.0. In other words, the transistor 112 turns OFF and transistors 118 and 120 turn ON, and charge is transferred from the supply voltage source V.sub.CC through the transistor 120 to the capacitor 110 and charge is transferred from the capacitor 116 through the transistor 118 to the load capacitor C.sub.L. As seen in FIG. 2, from the time t.sub.1, to a time t.sub.2 the voltage at the node 106 increases as the capacitor 110 is charging and the voltages on nodes 114 and 108 decrease and increase, respectively, as charge is transferred from the capacitor 116 to the load capacitor C.sub.L. At the time t.sub.2, the CLK and CLK signals again go high and low, respectively, and the charge pump circuit 100 operates as previously described at the time t.sub.0.
The charge pump circuit 100 continues operating in this manner during the normal mode, pumping charge from the supply voltage source V.sub.CC to the successive capacitors 110, 116, and C.sub.L to develop the desired pumped voltage V.sub.PD across the capacitor C.sub.L. When the pumped output voltage V.sub.P becomes greater than the desired voltage V.sub.PD, the charge pump circuit 100 commences operation in the power-savings mode of operation, which occurs at a time t.sub.3 in FIG. 2. In response to the pumped output voltage V.sub.P becoming greater than the desired voltage V.sub.PD, the external control circuit drives the REGOUT signal active high, causing the switching circuit 126 to present a high impedance so that the OCLK signal no longer clocks the clocking-latching circuit 128 which, in tun, no longer clocks the voltage-boosting stages 102 and 104. As a result, the CLK and CLK signals remain in their previous latched states until the pumped output voltage V.sub.P is less than V.sub.PD. This is seen in the example of FIG. 2 at a time t.sub.4 when, although the OCLK signal goes high, the CLK and CLK signals remain low and high, respectively, since OCLK signal is not applied to the clocking-latching circuit 128.
Once the pumped output voltage V.sub.P becomes less than V.sub.PD, the control circuit drives the REGOUT signal inactive low and the charge pump circuit 100 again commences operation in the normal mode. As will be understood by those skilled in the art, the switching circuit 126 enables the charge pump circuit 100 to very quickly switch into the normal mode of operation since the ring oscillator 124 continually generates the OCLK signal. In other words, since the ring oscillator 124 continuously generates the OCLK signal, transition from the power-savings to normal mode is delayed only by the switching time of the circuit 126, which is very fast. In contrast, if the ring oscillator 124 was turned ON and OFF responsive to the REGOUT signal, the settling time (i.e., the time for the CLK, CLK signals to stabilize) of the oscillator when turned back ON is much greater than the switching time of the circuit 126. As a result, in this situation the voltage V.sub.P could continue to decrease during this settling time, thereby increasing the ripple of the voltage V.sub.P.
The power-savings mode of operation reduces the overall power consumption of the circuit 100 since the CLK and CLK signals do not clock the stages 102 and 104 when the voltage V.sub.P is greater than the desired voltage V.sub.PD. Although the overall power consumption of the circuit 100 is reduced and the switching circuit 126 alleviates some of the ripple introduced by switching between modes, operation in the power-savings mode introduces additional ripple of the pumped output voltage V.sub.P due to the transistor 118 in the final voltage-boosting stage 104 remaining turned ON during this mode of operation. More specifically, when the charge pump circuit 100 enters the power savings mode of operation the CLK and CLK signals have one of two states. If the CLK and CLK signals are high and low, respectively, when the REGOUT signal goes active to enter the power-savings mode, then the boosted gate signal V.sub.BG remains low during this mode and the transistor 118 is turned OFF. In this situation, the turned OFF transistor 118 isolates the output node 108 and the voltage V.sub.P is not affected by the voltage on the node 114.
In contrast, if the CLK and CLK signals are low and high, respectively, when the REGOUT signal goes active, the transistor 118 may remain turned ON during the power-savings mode thereby coupling the output node 108 to the node 114. As a result, the voltage on the node 114 affects the pumped output voltage V.sub.P in this situation. For example, as illustrated in FIG. 2, it is seen that when the REGOUT signal goes high at the time t.sub.3 the CLK and CLK signals are low and high, respectively, so the signal V.sub.BG is high turning ON the transistor 118. As seen after the time t.sub.3, the pumped output voltage V.sub.P continues to increase as charge is transferred from the capacitor 116 through the transistor 118 to the load capacitor C.sub.L. Thus, the pumped voltage V.sub.P undesirably increases after time t.sub.3 even though it is already greater than the desired voltage V.sub.PD, thereby increasing the ripple of the pumped output voltage.
There is a need for a charge pump circuit having a low power consumption and a reduced ripple of the generated pumped output voltage.